Revolutionizing Semiconductor Chip Design with Generative AI
Traditional semiconductor chip design typically begins with a lengthy and often arduous process of specification definition, RTL model creation and documentation, before engineering teams can set out on designing actual circuits. However, what if this IP creation and team-based design review phase could be cut down to a few weeks, rather than months, with literally hundreds of hours of design team meetings saved in the process?
This is the goal of a new “ChipGPT” type tool, that Cadence Design Systems is bringing to market, which employs Large Language Models and generative AI to do much of the heavy lifting in this early semiconductor definition and design verification phase.
As a new introductory component of its JedAI analytics suite for cross-platform design visualization, which is comprised of AI-enhanced tools for processes like static timing analysis and performance, power and area optimization of chip designs, Cadence has introduced a chip specification and pre-verification tool that is LLM-assisted for workflow automation of these critical first steps in semiconductor design definition and creation.
In fact, this new generative AI-assisted EDA tool could save hundreds of man-hours of engineering resources in design meetings alone, so much so that mixed-signal semiconductor leader, Rensas engaged early in a development process to collaborate with Cadence as one of the tool’s early adopters. “Ensuring alignment between specification and design is critical, and the cost of verification has increased with the complexity of design functions. Renesas and Cadence have collaborated to develop a novel approach to address this challenge by leveraging generative AI’s LLM capabilities, which significantly reduce the time from specification to final design by efficiently controlling design quality,” noted Renesas SVP and CTO, Shinichi Yoshioka.
I had a chance to ask Mr. Yoshioka for a few specifics about the company’s efforts with Cadence’s new technologies, and indeed the Renesas team is now utilizing the tool for automated check and check assist w/ generative AI, for more efficient and effective design, verification and review. Yoshioka-san observed that “…the automated check and check assist capabilities would help us avoid quality issue recurrences, which contributes to time-to-market acceleration.” Further on the subject, Yoshioka offered that, “We see Large Language Models as an important piece of the puzzle that will shape the future for semiconductor design processes.”
Though Yoshioka noted that current LLMs are not designed to fully understand and perform fully accurate arithmetic/logical operations, generative AI has once again proven itself capable of alleviating semiconductor design teams from large portions of iterative optimization and verification work.
It’s widely understood at this point, that machine learning is still very much in its infancy. And so it also seems logical that this new evolution of ChipGPT, so to speak, is also just getting warmed-up and these early results are indeed promising.
